[ DevCourseWeb.com ] VIVADO - Learn From The Beginning! (With PCIe Full Project)
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MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + .srt | Duration: 31 lectures (7h 52m) | Size: 3.91 GB
Learn how to use Vivado design suite to design Xilinx FPGA FROM ZERO using VHDL or VERILOG language!
What you'll learn:
How to use Vivado
Full Project with PCIe root complex to PCIe end point communication, how to setup the root complex and how to simulate the PCIe
Adding IP to your project.
Axi-Bus, Streamed and Memory-mapped IP's and differences.
Test Bench, what is it and how to write it
How to simulate Vivado projects, using the Modelsim tool or Vivado.
Zynq 7000, explained and implementation.
Connecting Axi Bus to Zynq7000 peripherals and between IPs.
Adding ILA ,integrated logic analyzer, the strongest tool for real-time debug.
How to open SDK project
More complex things you must know for using Vivado even in your working place as a professional!
Requirements
Having a PC with windows/Linux and internet connection.
Basic VHDL/Verilog Knowledge
Installing Xilinx's Vivado Design suite 2019, explained in the course.
Installing ModelSim simulation tool, explained in the course.
Description
In this course you will learn to develop FPGAs with VHDL language, FPGA is an integrated circuit - a chip that is making complex calculations in parallel and can be program by the developer. today can be found in every smart phone, cars, plans, most of your electronics have FPGA.
Today, working as a FPGA developer is the most profitable job in Hardware development. And is a profession in great demand in every big company: apple, microsoft, intel, amazon, google and so many others!
Use Winrar to Extract. And use a shorter path when extracting, such as C: drive
ALSO ANOTHER TIP: You Can Easily Navigate Using Winrar and Rename the Too Long File/ Folder Name if Needed While You Cannot in Default Windows Explorer. You are Welcome ! :)
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