Udemy - Verilog HDL Fundamentals for Digital Design and Verification

Verilog HDL Fundamentals for Digital Design and Verification



Genre: eLearning | MP4 | Video: h264, 1280x720 | Audio: AAC, 48.0 KHz
Language: English | Size: 3.36 GB | Duration: 5h 2m
Build a strong Verilog language foundation by implementing combinational / sequential digital circuits and testbenches
What you'll learn
Master the basics of Verilog language for designing synthesizable digital circuits for ASIC / FPGA
Differentiate between Verilog structural / dataflow / behavioral design styles and how / when to use them in Digital Design and Verification
Implement combinational and sequential digital circuits using Verilog HDL starting from schematics or functional specifications
Create and simulate a Verilog testbench for a digital circuit starting from its functional specifications
Examine the behavior of a digital circuit receiving stimulus in a testbench, using an industry-level simulator (free for academic purposes)
Explicit visual explanations for the 80+ downloadable code examples, circuits, and testbenches offering you increased retention and accelerated learning

Description
Are you a beginner or an enthusiastic hobbyist interested in digital circuits design using the Verilog Hardware Description Language? Did you try to learn Verilog HDL before, but found it very challenging? Are you curious if you have what it takes to become a digital chip designer? Then you're in the right place!

Verilog Hardware Description Language easy as A,B,C

You'll learn the basics of digital circuits theory and we'll focus most of our energy on implementing practical coding examples with real digital circuits using Verilog. You will graduate this course with a strong foundation in Verilog HDL for both Digital Design and Functional Verification.

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